#pragma once
#include <stdint.h>
//#include "simu_mcu582.h"

#define TMR0_3_IT_CYC_END     0x01  // 周期结束标志：捕捉-超时，定时-周期结束，PWM-周期结束
#define TMR0_3_IT_DATA_ACT    0x02  // 数据有效标志：捕捉-新数据，PWM-有效电平结束
#define TMR0_3_IT_FIFO_HF     0x04  // FIFO 使用过半：捕捉- FIFO>=4， PWM- FIFO<4
#define TMR1_2_IT_DMA_END     0x08  // DMA 结束，支持TMR1和TMR2
#define TMR0_3_IT_FIFO_OV     0x10  // FIFO 溢出：捕捉- FIFO满， PWM- FIFO空

#define CLK_SOURCE_PLL_60MHz 60
#define __INTERRUPT
#define __HIGH_CODE

#define GPIO_Pin_0      (0x00000001) /*!< Pin 0 selected */
#define GPIO_Pin_1      (0x00000002) /*!< Pin 1 selected */
#define GPIO_Pin_2      (0x00000004) /*!< Pin 2 selected */
#define GPIO_Pin_3      (0x00000008) /*!< Pin 3 selected */
#define GPIO_Pin_4      (0x00000010) /*!< Pin 4 selected */
#define GPIO_Pin_5      (0x00000020) /*!< Pin 5 selected */
#define GPIO_Pin_6      (0x00000040) /*!< Pin 6 selected */
#define GPIO_Pin_7      (0x00000080) /*!< Pin 7 selected */
#define GPIO_Pin_8      (0x00000100) /*!< Pin 8 selected */
#define GPIO_Pin_9      (0x00000200) /*!< Pin 9 selected */
#define GPIO_Pin_10     (0x00000400) /*!< Pin 10 selected */
#define GPIO_Pin_11     (0x00000800) /*!< Pin 11 selected */
#define GPIO_Pin_12     (0x00001000) /*!< Pin 12 selected */
#define GPIO_Pin_13     (0x00002000) /*!< Pin 13 selected */
#define GPIO_Pin_14     (0x00004000) /*!< Pin 14 selected */
#define GPIO_Pin_15     (0x00008000) /*!< Pin 15 selected */
#define GPIO_Pin_16     (0x00010000) /*!< Pin 16 selected */
#define GPIO_Pin_17     (0x00020000) /*!< Pin 17 selected */
#define GPIO_Pin_18     (0x00040000) /*!< Pin 18 selected */
#define GPIO_Pin_19     (0x00080000) /*!< Pin 19 selected */
#define GPIO_Pin_20     (0x00100000) /*!< Pin 20 selected */
#define GPIO_Pin_21     (0x00200000) /*!< Pin 21 selected */
#define GPIO_Pin_22     (0x00400000) /*!< Pin 22 selected */
#define GPIO_Pin_23     (0x00800000) /*!< Pin 23 selected */
#define GPIO_Pin_All    (0xFFFFFFFF) /*!< All pins selected */


typedef enum
{
	/* 校准精度越高，耗时越长 */
	Level_32 = 3, // 用时 1.2ms 1000ppm (32M 主频)  1100ppm (64M 主频)
	Level_64,     // 用时 2.2ms 800ppm  (32M 主频)  1000ppm (64M 主频)
	Level_128,    // 用时 4.2ms 600ppm  (32M 主频)  800ppm  (64M 主频)

} Cali_LevelTypeDef;
// @brief  32K时钟选择
typedef enum
{
	Clk32K_LSI = 0,
	Clk32K_LSE,
} LClk32KTypeDef;
typedef enum
{
	Period_0_125_S = 0, // 0.125s 周期
	Period_0_25_S,      // 0.25s 周期
	Period_0_5_S,       // 0.5s 周期
	Period_1_S,         // 1s 周期
	Period_2_S,         // 2s 周期
	Period_4_S,         // 4s 周期
	Period_8_S,         // 8s 周期
	Period_16_S,        // 16s 周期
} RTC_TMRCycTypeDef;

typedef enum IRQn
{
	Reset_IRQn = 1,
	NMI_IRQn = 2,      /*!<  Non Maskable Interrupt   */
	EXC_IRQn = 3,      /*!<  Exceptions Interrupt     */
	SysTick_IRQn = 12,	  /*!<  System timer Interrupt  */
	SWI_IRQn = 14,     /*!<  software Interrupt */
	TMR0_IRQn = 16,
	GPIO_A_IRQn = 17,
	GPIO_B_IRQn = 18,
	SPI0_IRQn = 19,
	BLEB_IRQn = 20,
	BLEL_IRQn = 21,
	USB_IRQn = 22,
	USB2_IRQn = 23,
	TMR1_IRQn = 24,
	TMR2_IRQn = 25,
	UART0_IRQn = 26,
	UART1_IRQn = 27,
	RTC_IRQn = 28,
	ADC_IRQn = 29,
	I2C_IRQn = 30,
	PWMX_SPI1_IRQn = 31,
	TMR3_IRQn = 32,
	UART2_IRQn = 33,
	UART3_IRQn = 34,
	WDOG_BAT_IRQn = 35
} IRQn_Type;
typedef enum
{
	HSE_RCur_75 = 0,
	HSE_RCur_100,
	HSE_RCur_125,
	HSE_RCur_150

} HSECurrentTypeDef;
typedef enum
{
	GPIO_ModeIN_Floating, //浮空输入
	GPIO_ModeIN_PU,       //上拉输入
	GPIO_ModeIN_PD,       //下拉输入
	GPIO_ModeOut_PP_5mA,  //推挽输出最大5mA
	GPIO_ModeOut_PP_20mA //推挽输出最大20mA
} GPIOModeTypeDef;
typedef enum
{
	GPIO_ITMode_LowLevel,  //低电平触发
	GPIO_ITMode_HighLevel, //高电平触发
	GPIO_ITMode_FallEdge,  //下降沿触发
	GPIO_ITMode_RiseEdge  //上升沿触发

} GPIOITModeTpDef;
typedef enum
{
	UART_1BYTE_TRIG = 0, // 1字节触发
	UART_2BYTE_TRIG,     // 2字节触发
	UART_4BYTE_TRIG,     // 4字节触发
	UART_7BYTE_TRIG,     // 7字节触发

} UARTByteTRIGTypeDef;
typedef enum
{
	DISABLE = 0,
	ENABLE = !DISABLE
} FunctionalState;
typedef enum
{
	RTC_TRIG_EVENT = 0, // RTC 触发事件
	RTC_TMR_EVENT,      // RTC 周期定时事件

} RTC_EVENTTypeDef;
typedef struct 
{
	uint32_t CTLR;
	uint32_t SR;
	uint64_t CNT;
	uint64_t CMP;
} SysTick_Type;
typedef enum
{
	SampleFreq_3_2 = 0, // 3.2M 采样频率
	SampleFreq_8,       // 8M 采样频率
	SampleFreq_5_33,    // 5.33M 采样频率
	SampleFreq_4,       // 4M 采样频率
} ADC_SampClkTypeDef;
typedef enum
{
	ADC_PGA_1_4 = 0, // -12dB, 1/4倍
	ADC_PGA_1_2,     // -6dB, 1/2倍
	ADC_PGA_0,       // 0dB, 1倍，无增益
	ADC_PGA_2,       // 6dB, 2倍
} ADC_SignalPGATypeDef;


//extern unsigned char simu_gpio_a[];
//extern unsigned char simu_gpio_b[];
extern unsigned char simu_register[];
extern SysTick_Type* SysTick;

#define R8_PA_PIN_0         (*((byte*)&simu_hw.gpioa + 0)) // RO, GPIO PA input byte 0
#define R8_PA_PIN_1         (*((byte*)&simu_hw.gpioa + 1)) // RO, GPIO PA input byte 1
#define R8_PA_OUT_0         (*((byte*)&simu_hw.gpioa + 0)) // RW, GPIO PA output byte 0
#define R8_PA_OUT_1         (*((byte*)&simu_hw.gpioa + 1)) // RW, GPIO PA output byte 1
#define R8_PA_DIR_0         (*((byte*)&simu_hw.gpioa_d + 0))  // RW, GPIO PA I/O direction byte 0
#define R8_PA_DIR_1         (*((byte*)&simu_hw.gpioa_d + 1))  // RW, GPIO PA I/O direction byte 1
							
#define R8_PB_PIN_0         (*((byte*)&simu_hw.gpiob + 0)) // RO, GPIO PB input byte 0
#define R8_PB_PIN_1         (*((byte*)&simu_hw.gpiob + 1)) // RO, GPIO PB input byte 1
#define R8_PB_PIN_2         (*((byte*)&simu_hw.gpiob + 2)) // RO, GPIO PB input byte 2
#define R8_PB_OUT_0         (*((byte*)&simu_hw.gpiob + 0)) // RW, GPIO PB output byte 0
#define R8_PB_OUT_1         (*((byte*)&simu_hw.gpiob + 1)) // RW, GPIO PB output byte 1
#define R8_PB_OUT_2         (*((byte*)&simu_hw.gpiob + 2)) // RW, GPIO PB output byte 2
#define R8_PB_DIR_0         (*((byte*)&simu_hw.gpiob_d + 0))  // RW, GPIO PA I/O direction byte 0
#define R8_PB_DIR_1         (*((byte*)&simu_hw.gpiob_d + 1))  // RW, GPIO PA I/O direction byte 1
#define R8_PB_DIR_2         (*((byte*)&simu_hw.gpiob_d + 2))  // RW, GPIO PA I/O direction byte 0

#define GPIOA_ResetBits(pin)      (simu_hw.gpioa &= (~pin)) 
#define GPIOA_SetBits(pin)        (simu_hw.gpioa |= pin)
#define GPIOA_InverseBits(pin)    (simu_hw.gpioa ^= pin)
#define GPIOA_ReadPortPin(pin)    (((simu_hw.gpioa & pin) != 0)? 1 : 0)
#define GPIOB_ResetBits(pin)      (simu_hw.gpiob &= (~pin))
#define GPIOB_SetBits(pin)        (simu_hw.gpiob |= pin)
#define GPIOB_InverseBits(pin)    (simu_hw.gpiob ^= pin)
#define GPIOB_ReadPortPin(pin)    (((simu_hw.gpiob & pin) != 0)? 1 : 0)

#define R32_SAFE_ACCESS     (*((uint8_t*)simu_register)) // RW, safe accessing
#define R8_SAFE_ACCESS_SIG  (*((uint8_t*)simu_register + 1))  // WO, safe accessing sign register, must write SAFE_ACCESS_SIG1 then SAFE_ACCESS_SIG2 to enter safe accessing mode
#define  RB_SAFE_ACC_MODE   0x03                      // RO, current safe accessing mode: 11=safe/unlocked (SAM), other=locked (00..01..10..11)
#define  RB_SAFE_ACC_ACT    0x08                      // RO, indicate safe accessing status now: 0=locked, read only, 1=safe/unlocked (SAM), write enabled
#define  RB_SAFE_ACC_TIMER  0x70                      // RO, safe accessing timer bit mask (16*clock number)
#define SAFE_ACCESS_SIG1    0x57                      // WO: safe accessing sign value step 1
#define SAFE_ACCESS_SIG2    0xA8                      // WO: safe accessing sign value step 2
#define SAFE_ACCESS_SIG0    0x00                      // WO: safe accessing sign value for disable
#define  RB_SLP_RTC_WAKE    0x08                      // RWA, enable RTC waking
#define  RB_SLP_GPIO_WAKE   0x10                      // RWA, enable GPIO waking
#define  RB_SLP_BAT_WAKE    0x20                      // RWA, enable BAT waking
#define  RB_WAKE_EV_MODE    0x40                      // RWA, event wakeup mode: 0=event keep valid for long time, 1=short pulse event
#define  RB_WAKE_DLY_MOD    0x03                      // RWA, wakeup delay time selection
/* System: real-time clock register */
#define  RB_RTC_TMR_CLR     0x10                      // RW, set 1 to clear RTC timer action flag, auto clear
#define  RB_RTC_TRIG_CLR    0x20                      // RW, set 1 to clear RTC trigger action flag, auto clear
#define  RB_RTC_TMR_FLAG    0x40                      // RO, RTC timer action flag
#define  RB_RTC_TRIG_FLAG   0x80                      // RO, RTC trigger action flag
#define  RB_RTC_TMR_MODE    0x07                      // RWA, RTC timer mode: 000=0.125S, 001=0.25S, 010=0.5S, 011=1S, 100=2S, 101=4S, 110=8S, 111=16S
#define  RB_RTC_IGNORE_B0   0x08                      // RWA, force ignore bit0 for trigger mode: 0=compare bit0, 1=ignore bit0
#define  RB_RTC_TMR_EN      0x10                      // RWA, RTC timer mode enable
#define  RB_RTC_TRIG_EN     0x20                      // RWA, RTC trigger mode enable
#define  RB_RTC_LOAD_LO     0x40                      // RWA, set 1 to load RTC count low word R32_RTC_CNT_32K, auto clear after loaded
#define  RB_RTC_LOAD_HI     0x80                      // RWA, set 1 to load RTC count high word R32_RTC_CNT_DAY, auto clear after loaded
#define  RB_PWR_XROM        0x01                      // RWA, power for flash ROM
#define  RB_PWR_RAM2K       0x02                      // RWA, power for retention 2KB SRAM
#define  RB_PWR_CORE        0x04                      // RWA, power retention for core and base peripherals
#define  RB_PWR_EXTEND      0x08                      // RWA, power retention for USB and BLE
#define  RB_PWR_RAM30K      0x10                      // RWA, power for main SRAM
#define  RB_PWR_SYS_EN      0x80                      // RWA, power for system
/* UART register address offset and bit define */
#define UART_FIFO_SIZE      8                         // UART FIFO size (depth)
#define UART_RECV_RDY_SZ    7                         // the max FIFO trigger level for UART receiver data available
#define UART_MCR            0
#define  RB_MCR_DTR         0x01                      // RW, UART0 control DTR
#define  RB_MCR_RTS         0x02                      // RW, UART0 control RTS
#define  RB_MCR_OUT1        0x04                      // RW, UART0 control OUT1
#define  RB_MCR_OUT2        0x08                      // RW, UART control OUT2
#define  RB_MCR_INT_OE      0x08                      // RW, UART interrupt output enable
#define  RB_MCR_LOOP        0x10                      // RW, UART0 enable local loop back
#define  RB_MCR_AU_FLOW_EN  0x20                      // RW, UART0 enable autoflow control
#define  RB_MCR_TNOW        0x40                      // RW, UART0 enable TNOW output on DTR pin
#define  RB_MCR_HALF        0x80                      // RW, UART0 enable half-duplex
#define UART_IER            1
#define  RB_IER_RECV_RDY    0x01                      // RW, UART interrupt enable for receiver data ready
#define  RB_IER_THR_EMPTY   0x02                      // RW, UART interrupt enable for THR empty
#define  RB_IER_LINE_STAT   0x04                      // RW, UART interrupt enable for receiver line status
#define  RB_IER_MODEM_CHG   0x08                      // RW, UART0 interrupt enable for modem status change
#define  RB_IER_DTR_EN      0x10                      // RW, UART0 DTR/TNOW output pin enable
#define  RB_IER_RTS_EN      0x20                      // RW, UART0 RTS output pin enable
#define  RB_IER_TXD_EN      0x40                      // RW, UART TXD pin enable
#define  RB_IER_RESET       0x80                      // WZ, UART software reset control, high action, auto clear
#define UART_FCR            2
#define  RB_FCR_FIFO_EN     0x01                      // RW, UART FIFO enable
#define  RB_FCR_RX_FIFO_CLR 0x02                      // WZ, clear UART receiver FIFO, high action, auto clear
#define  RB_FCR_TX_FIFO_CLR 0x04                      // WZ, clear UART transmitter FIFO, high action, auto clear
#define  RB_FCR_FIFO_TRIG   0xC0                      // RW, UART receiver FIFO trigger level: 00-1byte, 01-2bytes, 10-4bytes, 11-7bytes
#define UART_LCR            3
#define  RB_LCR_WORD_SZ     0x03                      // RW, UART word bit length: 00-5bit, 01-6bit, 10-7bit, 11-8bit
#define  RB_LCR_STOP_BIT    0x04                      // RW, UART stop bit length: 0-1bit, 1-2bit
#define  RB_LCR_PAR_EN      0x08                      // RW, UART parity enable
#define  RB_LCR_PAR_MOD     0x30                      // RW, UART parity mode: 00-odd, 01-even, 10-mark, 11-space
#define  RB_LCR_BREAK_EN    0x40                      // RW, UART break control enable
#define  RB_LCR_DLAB        0x80                      // RW, UART reserved bit
#define  RB_LCR_GP_BIT      0x80                      // RW, UART general purpose bit
#define UART_IIR            4
#define  RB_IIR_NO_INT      0x01                      // RO, UART no interrupt flag: 0=interrupt action, 1=no interrupt
#define  RB_IIR_INT_MASK    0x0F                      // RO, UART interrupt flag bit mask
#define  RB_IIR_FIFO_ID     0xC0                      // RO, UART FIFO enabled flag
#define UART_LSR            5
#define  RB_LSR_DATA_RDY    0x01                      // RO, UART receiver fifo data ready status
#define  RB_LSR_OVER_ERR    0x02                      // RZ, UART receiver overrun error
#define  RB_LSR_PAR_ERR     0x04                      // RZ, UART receiver parity error
#define  RB_LSR_FRAME_ERR   0x08                      // RZ, UART receiver frame error
#define  RB_LSR_BREAK_ERR   0x10                      // RZ, UART receiver break error
#define  RB_LSR_TX_FIFO_EMP 0x20                      // RO, UART transmitter fifo empty status
#define  RB_LSR_TX_ALL_EMP  0x40                      // RO, UART transmitter all empty status
#define  RB_LSR_ERR_RX_FIFO 0x80                      // RO, indicate error in UART receiver fifo
#define UART_MSR            6
#define  RB_MSR_CTS_CHG     0x01                      // RZ, UART0 CTS changed status, high action
#define  RB_MSR_DSR_CHG     0x02                      // RZ, UART0 DSR changed status, high action
//#define  RB_MSR_RI_CHG      0x04                      // RZ, UART0 RI changed status, high action
//#define  RB_MSR_DCD_CHG     0x08                      // RZ, UART0 DCD changed status, high action
#define  RB_MSR_CTS         0x10                      // RO, UART0 CTS action status
#define  RB_MSR_DSR         0x20                      // RO, UART0 DSR action status
//#define  RB_MSR_RI          0x40                      // RO, UART0 RI action status
//#define  RB_MSR_DCD         0x80                      // RO, UART0 DCD action status
#define UART_RBR            8
#define UART_THR            8
#define UART_RFC            0x0A
#define UART_TFC            0x0B
#define UART_DLL            0x0C
#define UART_DLM            0x0D
#define UART_DIV            0x0E
#define UART_ADR            0x0F

/* UART interrupt identification values for IIR bits 3:0 */
#define UART_II_SLV_ADDR    0x0E                      // RO, UART0 slave address match
#define UART_II_LINE_STAT   0x06                      // RO, UART interrupt by receiver line status
#define UART_II_RECV_RDY    0x04                      // RO, UART interrupt by receiver data available
#define UART_II_RECV_TOUT   0x0C                      // RO, UART interrupt by receiver fifo timeout
#define UART_II_THR_EMPTY   0x02                      // RO, UART interrupt by THR empty
#define UART_II_MODEM_CHG   0x00                      // RO, UART0 interrupt by modem status change
#define UART_II_NO_INTER    0x01                      // RO, no UART interrupt is pending
/* System: I/O pin configuration register */
#define  RB_PIN_TMR0        0x01                      // RW, TMR0 alternate pin enable: 0=TMR0/PWM0/CAP0 on PA[9], 1=TMR0_/PWM0_/CAP0_ on PB[23]
#define  RB_PIN_TMR1        0x02                      // RW, TMR1 alternate pin enable: 0=TMR1/PWM1/CAP1 on PA[10], 1=TMR1_/PWM1_/CAP1_ on PB[10]
#define  RB_PIN_TMR2        0x04                      // RW, TMR2 alternate pin enable: 0=TMR2/PWM2/CAP2 on PA[11], 1=TMR2_/PWM2_/CAP2_ on PB[11]
#define  RB_PIN_TMR3        0x08                      // RW, TMR3 alternate pin enable: 0=TMR3/PWM3/CAP3 on PA[2], 1=TMR3_/PWM3_/CAP3_ on PB[22]
#define  RB_PIN_UART0       0x10                      // RW, RXD0/TXD0 alternate pin enable: 0=RXD0/TXD0 on PB[4]/PB[7], 1=RXD0_/TXD0_ on PA[15]/PA[14]
#define  RB_PIN_UART1       0x20                      // RW, RXD1/TXD1 alternate pin enable: 0=RXD1/TXD1 on PA[8]/PA[9], 1=RXD1_/TXD1_ on PB[12]/PB[13]
#define  RB_PIN_UART2       0x40                      // RW, RXD2/TXD2 alternate pin enable: 0=RXD2/TXD2 on PA[6]/PA[7], 1=RXD2_/TXD2_ on PB[22]/PB[23]
#define  RB_PIN_UART3       0x80                      // RW, RXD3/TXD3 alternate pin enable: 0=RXD3/TXD3 on PA[4]/PA[5], 1=RXD3_/TXD3_ on PB[20]/PB[21]
#define  RB_PIN_SPI0        0x100                     // RW, SCS/SCK0/MOSI/MISO alternate pin enable: 0=SCS/SCK0/MOSI/MISO on PA[12]/PA[13]/PA[14]/PA[15], 1=SCS_/SCK0_/MOSI_/MISO_ on PB[12]/PB[13]/PB[14]/PB[15]
#define  RB_PIN_PWMX        0x400                     // RW, PWM4/PWM5/PWM7/PWM8/PWM9 alternate pin enable: 0=PWM4/5/7/8/9 on PA[12]/PA[13]/PB[4]/PB[6]/PB[7], 1=PWM4/5/7/8/9 on PA[6]/PA[7]/PB[1]/PB[2]/P[3]
#define  RB_PIN_I2C         0x800                     // RW, SCL/SDA alternate pin enable: 0=SCL/SDA on PB[13]/PB[12], 1=SCL_/SDA_ on PB[21]/PB[20]
#define  RB_PIN_MODEM       0x1000                    // RW, DSR/DTR alternate pin enable: 0=DSR/DTR on PB[1]/PB[5], 1=DSR_/DTR_ on PB[14]/PB[15]
#define  RB_PIN_INTX        0x2000                    // RW, interrupt INT24/INT25 alternate pin enable: 0=INT24/INT25 on PB[8]/PB[9], 1=INT24_/INT25_ on PB[22]/PB[23]
#define  RB_PIN_U0_INV      0x4000                    // RW, RXD0/RXD0_/TXD0/TXD0_ invert input/output enable: 0=normal input/output, 1=RXD invert input, TXD invert output
#define  RB_RF_ANT_SW_EN    0x8000                    // RW, RF antenna switch control output enable: 0=disable output, 1=output on PB[16]/PB[17]/PB[18]/PB[19]/PB[20]/PB[21]
#define  RB_PIN_ADC8_9_IE   0x01                      // RW, ADC/TouchKey channel 9/8 digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_ADC6_7_IE   0x02                      // RW, ADC/TouchKey channel 7/6 digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_ADC10_IE    0x04                      // RW, ADC/TouchKey channel 10 digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_ADC11_IE    0x08                      // RW, ADC/TouchKey channel 11 digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_USB2_DP_PU  0x10                      // RW, USB2 UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode
#define  RB_PIN_USB2_IE     0x20                      // RW, USB2 analog I/O enable: 0=analog I/O disable, 1=analog I/O enable
#define  RB_PIN_USB_DP_PU   0x40                      // RW, USB UDP internal pullup resistance enable: 0=enable/disable by RB_UC_DEV_PU_EN, 1=enable pullup, replace RB_UC_DEV_PU_EN under sleep mode
#define  RB_PIN_USB_IE      0x80                      // RW, USB analog I/O enable: 0=analog I/O disable, 1=analog I/O enable
#define  RB_PIN_ADC0_IE     0x0200                    // RW, ADC/TouchKey channel 0 digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_ADC1_IE     0x0400                    // RW, ADC/TouchKey channel 1 digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_ADC12_IE    0x0800                    // RW, ADC/TouchKey channel 12 digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_ADC13_IE    0x1000                    // RW, ADC/TouchKey channel 13 digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_XT32K_IE    0x2000                    // RW, external 32KHz oscillator digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_ADC2_3_IE   0x4000                    // RW, ADC/TouchKey channel 2/3 digital input disable: 0=digital input enable, 1=digital input disable
#define  RB_PIN_ADC4_5_IE   0x8000                    // RW, ADC/TouchKey channel 4/5 digital input disable: 0=digital input enable, 1=digital input disable
/* System: ADC and Touch-key register */
#define  RB_ADC_CH_INX      0x0F                      // RW, ADC input channel index
#define  RB_ADC_POWER_ON    0x01                      // RW, ADC power control: 0=power down, 1=power on
#define  RB_ADC_BUF_EN      0x02                      // RW, ADC input buffer enable 
#define  RB_ADC_DIFF_EN     0x04                      // RW, ADC input channel mode: 0=single-end, 1=differnetial
#define  RB_ADC_OFS_TEST    0x08                      // RW, enable ADC offset test mode: 0=normal mode, 1=short to test offset
#define  RB_ADC_PGA_GAIN    0x30                      // RW, set ADC input PGA gain: 00=-12dB, 01=-6dB, 10=0dB, 11=6dB
#define  RB_ADC_CLK_DIV     0xC0                      // RW, select ADC clock frequency: 00=3.2MHz, 01=8MHz, 10=5.33MHz, 11=4MHz
#define  RB_ADC_START       0x01                      // RW, ADC convert start control: 0=stop ADC convert, 1=start an ADC convert, auto clear
#define  RB_ADC_EOC_X       0x80                      // RO, end of ADC conversion flag
#define  RB_TEM_SEN_PWR_ON  0x80                      // RW, temperature sensor power control: 0=power down, 1=power on
#define  RB_ADC_DATA        0x0FFF                    // RO, ADC conversion data
#define  RB_ADC_IF_EOC      0x80                      // RO, ADC conversion interrupt flag: 0=free or converting, 1=end of conversion, interrupt action, auto ADC or write R8_ADC_CONVERT or write R8_TKEY_CONVERT to clear flag
#define  RB_TKEY_CHARG_CNT  0x1F                      // RW, Touchkey charge count
#define  RB_TKEY_DISCH_CNT  0xE0                      // RW, Touchkey discharge count
#define  RB_TKEY_START      0x01                      // RW, Touchkey convert start control: 0=stop Touchkey convert, 1=start a Touchkey convert, auto clear
#define  RB_TKEY_PWR_ON     0x01                      // RW, Touchkey power on: 0=power down, 1=power on
#define  RB_TKEY_CURRENT    0x02                      // RW, Touchkey charge current selection: 0=35uA, 1=70uA
#define  RB_TKEY_DRV_EN     0x04                      // RW, Touchkey drive shield enable
#define  RB_TKEY_PGA_ADJ    0x08                      // RW, ADC input PGA speed selection: 0=slow, 1=fast
#define  RB_ADC_DMA_ENABLE  0x01                      // RW, ADC DMA enable
#define  RB_ADC_DMA_LOOP    0x04                      // RW, ADC DMA address loop enable
#define  RB_ADC_IE_DMA_END  0x08                      // RW, enable interrupt for ADC DMA completion
#define  RB_ADC_IE_EOC      0x10                      // RW, enable interrupt for end of ADC conversion
#define  RB_ADC_CONT_EN     0x40                      // RW, enable contineous conversion ADC
#define  RB_ADC_AUTO_EN     0x80                      // RW, enable auto continuing ADC for DMA
#define  RB_ADC_IF_DMA_END  0x08                      // RW1, interrupt flag for ADC DMA completion
#define  RB_ADC_IF_END_ADC  0x10                      // RW1, interrupt flag for end of ADC conversion, DMA for auto ADC or write R8_ADC_CONVERT to clear flag

#define SAFEOPERATE  {} 
#define R8_WDOG_COUNT       (*((uint8_t*)simu_register + 2))  // RW, watch-dog count, count by clock frequency Fsys/131072
#define R8_SLP_WAKE_CTRL	(*((uint8_t*)simu_register + 3))
#define R8_RTC_MODE_CTRL	(*((uint8_t*)simu_register + 4))
#define R8_UART0_FCR	(*((uint8_t*)simu_register + 5))
#define R8_UART0_LCR	(*((uint8_t*)simu_register + 6))
#define R8_UART0_IER	(*((uint8_t*)simu_register + 7))
#define R8_UART0_DIV	(*((uint8_t*)simu_register + 8))
#define R8_UART1_FCR	(*((uint8_t*)simu_register + 9))
#define R8_UART1_LCR	(*((uint8_t*)simu_register + 10))
#define R8_UART1_IER	(*((uint8_t*)simu_register + 11))
#define R8_UART1_DIV	(*((uint8_t*)simu_register + 12))
#define R8_UART0_RBR	(*((uint8_t*)simu_register + 13))
#define R8_UART1_RBR	(*((uint8_t*)simu_register + 14))
#define R8_UART2_RBR	(*((uint8_t*)simu_register + 15))
#define R8_UART0_RFC	(*((uint8_t*)simu_register + 16))
#define R8_UART1_RFC	(*((uint8_t*)simu_register + 17))
#define R8_UART2_RFC	(*((uint8_t*)simu_register + 18))
#define R32_ADC_CTRL	(*((uint8_t*)simu_register + 19)) // RW, ADC control
#define R8_TKEY_CONVERT     (*((uint8_t*)simu_register + 20)) // RW, Touchkey convert control
#define R8_ADC_CHANNEL      (*((uint8_t*)simu_register + 21)) // RW, ADC input channel selection
#define R8_ADC_CFG          (*((uint8_t*)simu_register + 22)) // RW, ADC configure
#define R8_ADC_CONVERT      (*((uint8_t*)simu_register + 23)) // RW, ADC convert control
#define R8_TEM_SENSOR       (*((uint8_t*)simu_register + 24)) // RW, temperature sensor control
#define R32_ADC_DATA        (*((uint8_t*)simu_register + 25)) // RO, ADC data and status
#define R16_ADC_DATA        (*((uint8_t*)simu_register + 26)) // RO, ADC data
#define R8_ADC_INT_FLAG     (*((uint8_t*)simu_register + 27)) // RO, ADC interrupt flag register
#define R32_TKEY_CTRL       (*((uint8_t*)simu_register + 28)) // RW, Touchkey control
#define R8_TKEY_COUNT       (*((uint8_t*)simu_register + 29)) // RW, Touchkey charge and discharge count
#define R8_TKEY_CFG         (*((uint8_t*)simu_register + 30)) // RW, Touchkey configure
#define R32_ADC_DMA_CTRL    (*((uint8_t*)simu_register + 31)) // RW, ADC DMA control
#define R8_ADC_CTRL_DMA     (*((uint8_t*)simu_register + 32)) // RW, ADC DMA control
#define R8_ADC_DMA_IF       (*((uint8_t*)simu_register + 33)) // RW1, ADC interrupt flag
#define ADC_ChannelCfg(d)      (R8_ADC_CHANNEL = d)

#define R8_RESET_STATUS		(*((uint8_t*)simu_register + 34)) // RW1, ADC interrupt flag

#define __I    volatile const /*!< defines 'read only' permissions     */
#define __O    volatile  /*!< defines 'write only' permissions     */
#define __IO   volatile  /*!< defines 'read / write' permissions   */
#define RV_STATIC_INLINE    static inline
/* memory mapped structure for Program Fast Interrupt Controller (PFIC) */
typedef struct
{
	__I uint32_t  ISR[8];           // 0
	__I uint32_t  IPR[8];           // 20H
	__IO uint32_t ITHRESDR;         // 40H
	uint8_t       RESERVED[4];      // 44H
	__O uint32_t  CFGR;             // 48H
	__I uint32_t  GISR;             // 4CH
	__IO uint8_t  IDCFGR[4];        // 50H
	uint8_t       RESERVED0[0x0C];  // 54H
	__IO uint32_t FIADDRR[4];       // 60H
	uint8_t       RESERVED1[0x90];  // 70H
	__O uint32_t  IENR[8];          // 100H
	uint8_t       RESERVED2[0x60];  // 120H
	__O uint32_t  IRER[8];          // 180H
	uint8_t       RESERVED3[0x60];  // 1A0H
	__O uint32_t  IPSR[8];          // 200H
	uint8_t       RESERVED4[0x60];  // 220H
	__O uint32_t  IPRR[8];          // 280H
	uint8_t       RESERVED5[0x60];  // 2A0H
	__IO uint32_t IACTR[8];         // 300H
	uint8_t       RESERVED6[0xE0];  // 320H
	__IO uint8_t  IPRIOR[256];      // 400H
	uint8_t       RESERVED7[0x810]; // 500H
	__IO uint32_t SCTLR;            // D10H
} PFIC_Type;
typedef enum
{
	Short_Delay = 0,
	Long_Delay,

} WakeUP_ModeypeDef;
#define R8_RTC_FLAG_CTRL    (*((uint8_t*)simu_register + 34)) // R8_RTC_FLAG_CTRL
#define R8_XT32K_TUNE    (*((uint8_t*)simu_register + 35)) // R8_XT32K_TUNE
#define R8_XT32M_TUNE    (*((uint8_t*)simu_register + 36)) // R8_XT32M_TUNE
#define R8_BAT_DET_CTRL    (*((uint8_t*)simu_register + 37)) // R8_BAT_DET_CTRL
#define R16_RTC_CNT_32K    (*((uint16_t*)simu_register + 38)) // R16_RTC_CNT_32K
#define R16_POWER_PLAN (*((uint16_t*)simu_register + 40)) // R16_POWER_PLAN
#define R8_SLP_POWER_CTRL (*((uint8_t*)simu_register + 42)) // R8_SLP_POWER_CTRL
#define R8_PLL_CONFIG (*((uint8_t*)simu_register + 44)) // R8_PLL_CONFIG
#define R8_RST_WDOG_CTRL (*((uint8_t*)simu_register + 45)) // R8_RST_WDOG_CTRL
#define R16_PA_INT_EN (*((uint16_t*)simu_register + 46)) // R16_PA_INT_EN
#define R16_INT32K_TUNE		(*((uint16_t*)simu_register + 48)) // R16_INT32K_TUNE
#define R16_PB_INT_EN (*((uint16_t*)simu_register + 50)) // R16_PA_INT_EN

#define PFIC                    ((PFIC_Type *)simu_register + 256)

#define RB_PWR_DCDC_EN 0x0200
#define RB_PWR_DCDC_PRE 0x0400
#define RB_PWR_PLAN_EN 0x1000 
#define RB_PWR_MUST_0010 0x04
#define RB_RAM_RET_LV 0x40
#define RB_SOFTWARE_RESET 0x01

#define ADC_ChannelCfg(d)      (R8_ADC_CHANNEL = d)

#ifndef EEPROM_PAGE_SIZE
#define EEPROM_PAGE_SIZE    256                       // Flash-ROM & Data-Flash page size for writing
#define EEPROM_BLOCK_SIZE   4096                      // Flash-ROM & Data-Flash block size for erasing
#define EEPROM_MIN_ER_SIZE  EEPROM_PAGE_SIZE          // Data-Flash minimal size for erasing
//#define EEPROM_MIN_ER_SIZE  EEPROM_BLOCK_SIZE         // Flash-ROM  minimal size for erasing
#define EEPROM_MIN_WR_SIZE  1                         // Data-Flash minimal size for writing
#define EEPROM_MAX_SIZE     0x8000                    // Data-Flash maximum size, 32KB
#endif
#ifndef FLASH_MIN_WR_SIZE
#define FLASH_MIN_WR_SIZE   4                         // Flash-ROM minimal size for writing
#endif
#ifndef FLASH_ROM_MAX_SIZE
#define FLASH_ROM_MAX_SIZE  0x070000                  // Flash-ROM maximum program size, 448KB
#endif


extern void SetSysClock(int x);
extern void SysTick_Config(int x);
extern void DelayMs(int x);
extern void LClk32K_Select(int x);
extern void PFIC_EnableIRQ(int x);
extern void SYS_RecoverIrq(uint32_t irq_status);
extern void GPIOA_ModeCfg(uint32_t pin, GPIOModeTypeDef mode);
extern void GPIOB_ModeCfg(uint32_t pin, GPIOModeTypeDef mode);
extern void GPIOA_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode);
extern void GPIOB_ITModeCfg(uint32_t pin, GPIOITModeTpDef mode);
extern void GPIOPinRemap(int x, int y);
extern void GPIOA_ClearITFlagBit(int x);
extern void GPIOB_ClearITFlagBit(int x);
extern void RTC_TMRFunCfg(int x);
extern void RTC_ClearITFlag(RTC_EVENTTypeDef f);
extern uint16_t GPIOA_ReadITFlagPort(void);
extern uint16_t GPIOB_ReadITFlagPort(void);

extern void UART0_DefInit();
extern void UART1_DefInit();
extern void UART2_DefInit();
extern void UART0_BaudRateCfg(int x);
extern void UART1_BaudRateCfg(int x);
extern void UART2_BaudRateCfg(int x);
extern void UART0_ByteTrigCfg(int x);
extern void UART1_ByteTrigCfg(int x);
extern void UART2_ByteTrigCfg(int x);
extern void UART0_INTCfg(int x);
extern void UART1_INTCfg(int x);
extern void UART2_INTCfg(int x);
extern void WWDG_ResetCfg(int x);
extern uint8_t RTC_GetITFlag(RTC_EVENTTypeDef f);
extern void LowPower_Sleep(uint8_t rm);
extern void HSECFG_Current(int x);
extern void ADC_ExtSingleChSampInit(ADC_SampClkTypeDef sp, ADC_SignalPGATypeDef ga);
extern signed short ADC_DataCalib_Rough(void); // 采样数据粗调,获取偏差值
extern void Calibration_LSI(int x);
extern int GetSysClock(void);

extern void UART0_SendString(uint8_t* buf, uint16_t l);

extern void SYS_DisableAllIrq(uint32_t* pirqv);
extern void SYS_ResetExecute(void);
extern void __WFE(void);
extern void DelayUs(int x);
extern void PWR_PeriphWakeUpCfg(FunctionalState s, uint8_t perph, WakeUP_ModeypeDef mode);
extern void WWDG_ITCfg(FunctionalState s);
extern uint32_t FLASH_EEPROM_CMD(uint8_t cmd, uint32_t StartAddr, void* Buffer, uint32_t Length);
extern void sys_safe_access_enable(void);
extern void sys_safe_access_disable(void);
extern void TMR0_TimerInit(uint32_t t);
#define TMR0_ITCfg(s, f) 
extern void PFIC_DisableIRQ(IRQn_Type IRQn);
#define TMR0_ClearITFlag(f) 

#define CMD_FLASH_ROM_SW_RESET 0
#define WWDG_SetCounter(c)    (R8_WDOG_COUNT = c)
#define FLASH_ROM_SW_RESET( )                       FLASH_EEPROM_CMD( CMD_FLASH_ROM_SW_RESET, 0, NULL, 0 )
